The following figure shows the slave logic.
Figure 1. AXI_Traffic_Generator Slave
- Slave-write
- The slave
AR
,AW
, andW
ports each have a FIFO to collect data from the switch. The output busesB
andR
also use a small FIFO to buffer their outgoing data. The write addresses from the AW bus then goes to an Aw_agen block which generates the proper MSTRAM addresses and writes the corresponding data word to the MSTRAM. After a transaction is complete, the ID information is passed to the B_track tracker which writes the completion ID to one of Bfifo0 to BFIFO3. These Bfifos then arbitrate to write the completions into the final Bfifo, allowing the creation of out-of-order write responses. - Slave-read
- Read addresses are placed in the Arfifo which then use the Ar_track tracker to
distribute the requests across Ar_agen0 to Ar_agen3. These generate the proper
addresses to the MSTRAM for each single request. The Ar_agen0 to Ar_agen3
arbitrates for access to the MSTRAM at each cycle in the Ar_sel block. The data
is placed in the small Rfifo and then driven to the switch on the
R
bus.
The following table shows the address map for different regions accessed by slave-write/slave-read.
Region | Description |
---|---|
0x0000_0000–0x0000_0FFF | Internal registers |
0x0000_1000–0x0000_17FF | PARAMRAM (2 KB) |
0x0000_8000–0x0000_9FFF | CMDRAM (8 KB) |
0x0000_A000–0x0000_AFFF | ADDRRAM (2 KB) |
0x0000_C000–0x0000_DFFF | MSTRAM (8 KB) |
Unused memory locations in the memory space (considering
0x00000000
to 0x0000FFFF
) with respect to the
preceding table are reserved; accessing these does not give any error response. Address
aliasing applied for memory space is defined in the preceding table except PARAMRAM.
For slave logic, the write interleaving depth is one.