Slave Modules - 3.0 English

AXI Traffic Generator LogiCORE IP Product Guide (PG125)

Document ID
PG125
Release Date
2023-10-18
Version
3.0 English

The following figure shows the slave logic.

Figure 1. AXI_Traffic_Generator Slave
Page-1 Box Awfifo Awfifo Box.2 Awfifo Awfifo Box.3 Wfifo Wfifo Box.4 Arfifo Arfifo Box.5 Ar_track Ar_track Box.6 B_track B_track Box.7 Bfifo Bfifo Box.8 MSTRAM MSTRAM Box.9 Rfifo Rfifo Box.10 Ar_sel Ar_sel Box.11 Bffo0 Bffo0 Box.12 Bffo1 Bffo1 Box.13 Bffo2 Bffo2 Box.14 Bffo3 Bffo3 Box.15 Ar_agen0 Ar_agen0 Box.16 Ar_agen1 Ar_agen1 Box.17 Ar_agen2 Ar_agen2 Box.18 Ar_agen3 Ar_agen3 Arrow LG Right Arrow LG Right.20 Arrow LG Right.21 Arrow LG Right.22 Arrow LG Right.23 Arrow LG Right.24 Arrow LG Right.25 Arrow LG Right.26 Arrow LG Right.27 Arrow LG Right.28 Arrow LG Right.29 Arrow LG Right.30 Arrow LG Right.31 Arrow LG Right.32 Arrow LG Right.33 Arrow LG Right.34 Arrow LG Right.35 Arrow LG Right.36 Arrow LG Right.37 Arrow LG Right.38 Arrow LG Right.39 Arrow LG Right.40 Arrow LG Right.41 Arrow LG Right.42 Arrow LG Right.43 Arrow LG Right.44 Arrow LG Right.45 Arrow LG Right.46 Text 8pt AW AW Text 8pt.48 W W Text 8pt.49 AR AR Text 8pt.50 B B Text 8pt.51 R R
Slave-write
The slave AR, AW, and W ports each have a FIFO to collect data from the switch. The output buses B and R also use a small FIFO to buffer their outgoing data. The write addresses from the AW bus then goes to an Aw_agen block which generates the proper MSTRAM addresses and writes the corresponding data word to the MSTRAM. After a transaction is complete, the ID information is passed to the B_track tracker which writes the completion ID to one of Bfifo0 to BFIFO3. These Bfifos then arbitrate to write the completions into the final Bfifo, allowing the creation of out-of-order write responses.
Slave-read
Read addresses are placed in the Arfifo which then use the Ar_track tracker to distribute the requests across Ar_agen0 to Ar_agen3. These generate the proper addresses to the MSTRAM for each single request. The Ar_agen0 to Ar_agen3 arbitrates for access to the MSTRAM at each cycle in the Ar_sel block. The data is placed in the small Rfifo and then driven to the switch on the R bus.

The following table shows the address map for different regions accessed by slave-write/slave-read.

Table 1. Slave-Write/Slave-Read Address Map
Region Description
0x0000_0000–0x0000_0FFF Internal registers
0x0000_1000–0x0000_17FF PARAMRAM (2 KB)
0x0000_8000–0x0000_9FFF CMDRAM (8 KB)
0x0000_A000–0x0000_AFFF ADDRRAM (2 KB)
0x0000_C000–0x0000_DFFF MSTRAM (8 KB)

Unused memory locations in the memory space (considering 0x00000000 to 0x0000FFFF) with respect to the preceding table are reserved; accessing these does not give any error response. Address aliasing applied for memory space is defined in the preceding table except PARAMRAM.

For slave logic, the write interleaving depth is one.