Slave Control register allows you to configure the slave interface of the AXI Traffic Generator to control/enable slave capabilities.
| Bits | Name | Reset Value | Access Type | Description |
|---|---|---|---|---|
| 31:20 | Reserved | N/A | N/A | Reserved |
| 19 | BLKRD | 0x0 | R/W |
Enable Block Read When set, slave reads are not processed if there are any pending writes. On completing each write, at least one read data is returned to prevent starvation. |
| 18 | DISEXCL | 0x0 | R/W |
Disable Exclusive Access When set, disables exclusive access support and error response ability for reads on Slave Error register. |
| 17 | WORDR | 0x0 | R/W |
Enable in Order Write Response When set, forces all BRESPs to be issued in the order the requests were received. |
| 16 | RORDR | 0x0 | R/W |
Enable in Order Read Response When set, forces all slave reads to be done in the order received. |
| 15 | ERREN | 0x0 | R/W |
Enable Error Generation When set, if any bit in Error Status register Bits[15:0] is set, then err_out is asserted. |
| 14:0 | Reserved | N/A | N/A | Reserved |