Revision History - 3.0 English - PG125

• Updated the invalid command information in Note 1 of Table 1-2.
• Added one Note under Table 2-3.

• Revision number advanced to 3.0 to align with the core version number.
• Updated the Output AXI4 Master Interface ports.

• Updated the figures to customize the core.
• Updated the User Parameters table.
• Added the LFSR implementation.

• Updated Master RAM section.
• Updated figures in Design Flow Steps chapter.
• Added Write Address Gen Seed and Data Generator Seed descriptions.
• Updated User Parameters table.

• Updated Features description in IP Facts.
• Updated AXI4 Traffic Generator Block Diagram.
• Added Address RAM section.
• Moved Performance and Resource Utilization to HTML.
• Updated Slave-Write/Slave-Read Address Map.
• Added description to Static Mode.
• Added description in High Level Traffic.
• Added Extended Transfer Length register to Streaming Mode Register Map.
• Updated figures in Design Flow Steps chapter.
• Added Address Width section in AXI4 Protocol section.
• Updated description in Static Mode Options section.
• Updated description in AXI Options section.
• Added parameters to Vivado IDE Parameter to User Parameter Relationship.

• Updated description in 011 in PARAMRAM Entry Control Signals table.
• Added description in PARAMRAM Opcodes section.
• Updated GUIs in Customizing and Generating the Core section.
• Added Repeat Count section.
• Added User Parameters section.
• Added UNISIM important note in Simulation section.

• Document updates only for revision change.
• Added note #4 in Table 1-2: CMDRAM Memory Format.
• Added notes to Table 1-3: PARAMRAM Entry Control Signals.
• Added note #2 to Table 1-6: OP_DELAY.
• Updated description in Static Mode section.
• Added Note and Important note in High Level Traffic section.
• Added note #3 to Table 2-3: AXI Traffic Generator I/O Signals.
• Added note to Table 2-19: Static Length.
• Updated Static Mode Options section.
• Updated AXI Options section.

• Updated Flexible data width capabilities and initialization support in Features section.
• Updated Basic description in AXI Traffic Generator Modes table.
• Updated AXI4-Stream Traffic Generator Block Diagram figure.
• Updated description in Command RAM section.
• Updated Bits[31:29] descriptions in PARAMRAM Entry Control Signals table.
• Updated Mstram_index offsets in Address Generation section.
• Updated CMDRAM and MSTRAM region in Slave-Write/Slave-Read Address Map table and description
• Added entries are 32-bit and Cascading ATGs description in System Init/ Test Mode section.
• Added High Level Traffic section and updated System Init/Test Mode status description in Programming Sequence section.
• Updated description in Advanced/Basic Mode without Processor Intervention section.
• Updated Resource Utilization section.
• Updated TDATA Width description in AXI4-Stream Protocol section.
• Updated Bit[19] descriptions in Master Control (0x00) register.
• Added Bit[2] in Streaming Config (0x34) register.
• Added User STRB/TKEEP Set 1 to 4 (0x40 to 0x4C) registers.
• Added traffic generation note to Streaming Control (0x30) and Static Mode Control (0x60) registers.
• Added IP integrator note in AXI4-Lite Protocol section.
• Added One-shot and Repetitive descriptions in Data Mode section.

• Added UltraScale support.
• Added loop enable Bit[19] to Master Control register 0x0.

Revision number advanced to 2.0 to align with core version number.

• Added new features in IP Facts.
• Added IP Integrator.
• Updated Overview chapter.
• Updated Resource Utilization in Product Specification chapter.
• Updated Streaming Config register.
• Updated Resets section.
• Updated Generating and Customizing the Core chapter.
• Added Simulation, Synthesis, Example Design, and Test Bench chapters.
• Added Port Changes in Migrating Appendix.
• Added Streaming mode to General Checks in Debug Appendix.