Register Space - 3.0 English

AXI Traffic Generator LogiCORE IP Product Guide (PG125)

Document ID
PG125
Release Date
2023-10-18
Version
3.0 English

The AXI Traffic Generator provides registers to control its behavior, provide status, or debug information, and control external signals. The register space is only partially decoded.

Important: All registers must be written with full-word writes.

Byte or halfword writes are interpreted as full-word writes (which can have unpredictable results). All bit descriptions use a little endian bit numbering, where 31 is the left-most or MSB, and Bit[0] is the right-most or LSB. All registers reset to default values (except for the read-only bits). Access to read-only registers issues an OKAY response.