Port Descriptions - 3.0 English

AXI Traffic Generator LogiCORE IP Product Guide (PG125)

Document ID
PG125
Release Date
2023-10-18
Version
3.0 English

The AXI Traffic Generator signals are listed and described in the following table.

Table 1. AXI Traffic Generator I/O Signals
Signal Name Interface I/O Description
System Signals
s_axi_aclk System I Clock
s_axi_aresetn System I Active-Low reset
irq_out System O Interrupt on traffic generation completion
err_out System O Error interrupt
done 2 System O Indicates the completion of the sequence for AXI4-Lite mode selection.
status System O

Status of the core operation in System Init/System Test mode. 32-bit Status Port Definition

   
31:16

Test Errors. Accumulates the number of errors seen during the genration of commands.

15:10 Reserved
9:2

Represents the COE index of the core it is currently processing. In case where the core repeatedly tries to issue the same command and exits after the maximum command retry count, this index is useful to debug.

1:0

Status of the Generation

00 = Reserved

01 = Pass

10 = Fail

11 = Hang

core_ext_start 4 System I Active-High pulse. Indicating the system to start generating or accepting the traffic.
core_ext_stop 4 System I Active-High pulse. Indicating the system to stop generating or accepting the traffic.
AXI4 Master Interface Signals
m_axi_* M_AXI AXI4 Master Interface signals. See Appendix A of the Vivado Design Suite: AXI Reference Guide (UG1037) for AXI4, AXI4-Lite, and AXI4-Stream Signals.
AXI4 Slave Interface Signals
s_axi_* S_AXI AXI4 Slave Interface signals. See Appendix A of the Vivado Design Suite: AXI Reference Guide (UG1037) for AXI4, AXI4-Lite, and AXI4-Stream Signals.
AXI4-Stream Interface Signals
m_axis_1_tready M_AXIS_MASTER I See AXIS Bus definition
m_axis_1_tvalid M_AXIS_MASTER O See AXIS Bus definition
m_axis_1_tlast M_AXIS_MASTER O See AXIS Bus definition
m_axis_1_tdata M_AXIS_MASTER O See AXIS Bus definition
m_axis_1_tstrb M_AXIS_MASTER O See AXIS Bus definition
m_axis_1_tkeep M_AXIS_MASTER O See AXIS Bus definition
m_axis_1_tuser M_AXIS_MASTER O See AXIS Bus definition
s_axis_1_tready S_AXIS_MASTER O See AXIS Bus definition
s_axis_1_tvalid S_AXIS_MASTER I See AXIS Bus definition
s_axis_1_tlast S_AXIS_MASTER I See AXIS Bus definition
s_axis_1_tdata S_AXIS_MASTER I See AXIS Bus definition
s_axis_1_tstrb S_AXIS_MASTER I See AXIS Bus definition
s_axis_1_tkeep S_AXIS_MASTER I See AXIS Bus definition
s_axis_1_tuser S_AXIS_MASTER I See AXIS Bus definition
s_axis_2_tready S_AXIS_SLAVE O See AXIS Bus definition
s_axis_2_tvalid S_AXIS_SLAVE I See AXIS Bus definition
s_axis_2_tlast S_AXIS_SLAVE I See AXIS Bus definition
s_axis_2_tdata S_AXIS_SLAVE I See AXIS Bus definition
s_axis_2_tstrb S_AXIS_SLAVE I See AXIS Bus definition
s_axis_2_tkeep S_AXIS_SLAVE I See AXIS Bus definition
s_axis_2_tuser S_AXIS_SLAVE I See AXIS Bus definition
m_axis_2_tready M_AXIS_SLAVE I See AXIS Bus definition
m_axis_2_tvalid M_AXIS_SLAVE O See AXIS Bus definition
m_axis_2_tlast M_AXIS_SLAVE O See AXIS Bus definition
m_axis_2_tdata M_AXIS_SLAVE O See AXIS Bus definition
m_axis_2_tstrb M_AXIS_SLAVE O See AXIS Bus definition
m_axis_2_tkeep M_AXIS_SLAVE O See AXIS Bus definition
m_axis_2_tuser M_AXIS_SLAVE O See AXIS Bus definition
AXI4-Lite Master Write Interface
m_axi_lite_ch*_awaddr M_AXI_LITE O See AXI4-Lite Bus definition
m_axi_lite_ch*_awprot M_AXI_LITE O See AXI4-Lite Bus definition
m_axi_lite_ch*_awvalid M_AXI_LITE O See AXI4-Lite Bus definition
m_axi_lite_ch*_awready M_AXI_LITE I See AXI4-Lite Bus definition
m_axi_lite_ch*_wdata M_AXI_LITE O See AXI4-Lite Bus definition
m_axi_lite_ch*_wstrb M_AXI_LITE O See AXI4-Lite Bus definition
m_axi_lite_ch*_wvalid M_AXI_LITE O See AXI4-Lite Bus definition
m_axi_lite_ch*_wready M_AXI_LITE I See AXI4-Lite Bus definition
m_axi_lite_ch*_bresp M_AXI_LITE I See AXI4-Lite Bus definition
m_axi_lite_ch*_bvalid M_AXI_LITE I See AXI4-Lite Bus definition
m_axi_lite_ch*_bready M_AXI_LITE O See AXI4-Lite Bus definition
  1. AXIS refers to streaming interface.
  2. The done port now qualifies the sequence completion in AXI4-Lite mode. irq_out is used in the earlier version for this purpose.
  3. In System INIT mode, M_AXI_LITE_CH* Read channel is not available as this mode is only intended to initialize the registers in the connected slave.
  4. The core_ext_start and core_ext_stop ports can be used to control the traffic generation or reception by the core, without any processor intervention.