The AXI Traffic Generator signals are listed and described in the following table.
Signal Name | Interface | I/O | Description | ||||||||||
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System Signals | |||||||||||||
s_axi_aclk | System | I | Clock | ||||||||||
s_axi_aresetn | System | I | Active-Low reset | ||||||||||
irq_out | System | O | Interrupt on traffic generation completion | ||||||||||
err_out | System | O | Error interrupt | ||||||||||
done 2 | System | O | Indicates the completion of the sequence for AXI4-Lite mode selection. | ||||||||||
status | System | O |
Status of the core operation in System Init/System Test mode. 32-bit Status Port Definition
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core_ext_start 4 | System | I | Active-High pulse. Indicating the system to start generating or accepting the traffic. | ||||||||||
core_ext_stop 4 | System | I | Active-High pulse. Indicating the system to stop generating or accepting the traffic. | ||||||||||
AXI4 Master Interface Signals | |||||||||||||
m_axi_* | M_AXI | AXI4 Master Interface signals. See Appendix A of the Vivado Design Suite: AXI Reference Guide (UG1037) for AXI4, AXI4-Lite, and AXI4-Stream Signals. | |||||||||||
AXI4 Slave Interface Signals | |||||||||||||
s_axi_* | S_AXI | AXI4 Slave Interface signals. See Appendix A of the Vivado Design Suite: AXI Reference Guide (UG1037) for AXI4, AXI4-Lite, and AXI4-Stream Signals. | |||||||||||
AXI4-Stream Interface Signals | |||||||||||||
m_axis_1_tready | M_AXIS_MASTER | I | See AXIS Bus definition | ||||||||||
m_axis_1_tvalid | M_AXIS_MASTER | O | See AXIS Bus definition | ||||||||||
m_axis_1_tlast | M_AXIS_MASTER | O | See AXIS Bus definition | ||||||||||
m_axis_1_tdata | M_AXIS_MASTER | O | See AXIS Bus definition | ||||||||||
m_axis_1_tstrb | M_AXIS_MASTER | O | See AXIS Bus definition | ||||||||||
m_axis_1_tkeep | M_AXIS_MASTER | O | See AXIS Bus definition | ||||||||||
m_axis_1_tuser | M_AXIS_MASTER | O | See AXIS Bus definition | ||||||||||
s_axis_1_tready | S_AXIS_MASTER | O | See AXIS Bus definition | ||||||||||
s_axis_1_tvalid | S_AXIS_MASTER | I | See AXIS Bus definition | ||||||||||
s_axis_1_tlast | S_AXIS_MASTER | I | See AXIS Bus definition | ||||||||||
s_axis_1_tdata | S_AXIS_MASTER | I | See AXIS Bus definition | ||||||||||
s_axis_1_tstrb | S_AXIS_MASTER | I | See AXIS Bus definition | ||||||||||
s_axis_1_tkeep | S_AXIS_MASTER | I | See AXIS Bus definition | ||||||||||
s_axis_1_tuser | S_AXIS_MASTER | I | See AXIS Bus definition | ||||||||||
s_axis_2_tready | S_AXIS_SLAVE | O | See AXIS Bus definition | ||||||||||
s_axis_2_tvalid | S_AXIS_SLAVE | I | See AXIS Bus definition | ||||||||||
s_axis_2_tlast | S_AXIS_SLAVE | I | See AXIS Bus definition | ||||||||||
s_axis_2_tdata | S_AXIS_SLAVE | I | See AXIS Bus definition | ||||||||||
s_axis_2_tstrb | S_AXIS_SLAVE | I | See AXIS Bus definition | ||||||||||
s_axis_2_tkeep | S_AXIS_SLAVE | I | See AXIS Bus definition | ||||||||||
s_axis_2_tuser | S_AXIS_SLAVE | I | See AXIS Bus definition | ||||||||||
m_axis_2_tready | M_AXIS_SLAVE | I | See AXIS Bus definition | ||||||||||
m_axis_2_tvalid | M_AXIS_SLAVE | O | See AXIS Bus definition | ||||||||||
m_axis_2_tlast | M_AXIS_SLAVE | O | See AXIS Bus definition | ||||||||||
m_axis_2_tdata | M_AXIS_SLAVE | O | See AXIS Bus definition | ||||||||||
m_axis_2_tstrb | M_AXIS_SLAVE | O | See AXIS Bus definition | ||||||||||
m_axis_2_tkeep | M_AXIS_SLAVE | O | See AXIS Bus definition | ||||||||||
m_axis_2_tuser | M_AXIS_SLAVE | O | See AXIS Bus definition | ||||||||||
AXI4-Lite Master Write Interface | |||||||||||||
m_axi_lite_ch*_awaddr | M_AXI_LITE | O | See AXI4-Lite Bus definition | ||||||||||
m_axi_lite_ch*_awprot | M_AXI_LITE | O | See AXI4-Lite Bus definition | ||||||||||
m_axi_lite_ch*_awvalid | M_AXI_LITE | O | See AXI4-Lite Bus definition | ||||||||||
m_axi_lite_ch*_awready | M_AXI_LITE | I | See AXI4-Lite Bus definition | ||||||||||
m_axi_lite_ch*_wdata | M_AXI_LITE | O | See AXI4-Lite Bus definition | ||||||||||
m_axi_lite_ch*_wstrb | M_AXI_LITE | O | See AXI4-Lite Bus definition | ||||||||||
m_axi_lite_ch*_wvalid | M_AXI_LITE | O | See AXI4-Lite Bus definition | ||||||||||
m_axi_lite_ch*_wready | M_AXI_LITE | I | See AXI4-Lite Bus definition | ||||||||||
m_axi_lite_ch*_bresp | M_AXI_LITE | I | See AXI4-Lite Bus definition | ||||||||||
m_axi_lite_ch*_bvalid | M_AXI_LITE | I | See AXI4-Lite Bus definition | ||||||||||
m_axi_lite_ch*_bready | M_AXI_LITE | O | See AXI4-Lite Bus definition | ||||||||||
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