PARAMRAM Opcodes - 3.0 English

AXI Traffic Generator LogiCORE IP Product Guide (PG125)

Document ID
PG125
Release Date
2023-10-18
Version
3.0 English

Each of the four commands uses 24 bits of op_control space to shape the command. Each of the four op_control fields is described in the following tables.

The OP_NOP command is ignored and the command within the CMDRAM is executed normally.

Table 1. OP_NOP
Bits Name Description
23:0 Unused N/A

The entire op_control field of 24 bits is used as a counter for repeating the command in the CMDRAM entry.

Table 2. OP_REPEAT
Bits Name Description
23:0 Repeat Count Command repeats this many times.

The entire op_control field of 24-bits is used as a delay counter for issuance of the command in the CMDRAM entry.

Table 3. OP_DELAY
Bits Name Description
23:0 Delay Count Command execution is delayed for this many cycles.
  1. Delay observed between two transactions ≥ the programmed value.
  2. If the programmed value is ≤ 6, the minimum delay observed is six clock cycles.
Table 4. OP_FIXEDREPEAT_DELAY
Bits Name Description
23:20 Addr Range Encoded Core issues a new random address within the range encoded below starting with base address you programmed.
Encoded Range (KB) Encoded Range (MB)
0 4 8 1
1 8 9 2
2 16 10 4
3 32 11 8
4 64 12 16
5 128 13 32
6 256 14 64
7 512 15 128
19:8 Delay Count Each command execution is delayed for this many cycles.
7:0 Delay Range Encoded Unused
  1. Delay observed between two transactions ≥ the programmed value.

PARAMRAM should be filled with valid data for the corresponding entry in the CMDRAM. CMDRAM should be filled with valid data until the first invalid command entry.

An example programming sequence is to generate a write transaction with 64 beats transferred to the slave every 5 µs. When the clock frequency is running at 100 MHz, you could have the awlen (other AXI parameters to be set as per requirement) set to 0x3F which corresponds to decimal value 63 to have 64 beats transferred in one transaction.

Also, you can have the PARAMRAM programmed to value 0x400001F4, which decodes as IP is in OP_DELAY mode. The minimum delay between two transactions is 1F4 cycles, which is 500 cycles. If you want the transaction to be repeated, the PARAMRAM can be programmed as 0x8001F400 to set IP in FIXEDREPEAT_DELAY mode. The repeat count would be dependent on the AMD Vivado™ IDE value selected.