PARAMRAM - 3.0 English

AXI Traffic Generator LogiCORE IP Product Guide (PG125)

Document ID
PG125
Release Date
2023-10-18
Version
3.0 English

The PARAMRAM extends the command programmability provided through command RAM by adding 32-bits to the decode of each command. The following figure shows how the PARAMRAM is addressed in relation to the CMDRAM. Only write access is allowed to the PARAMRAM from the slave interface. Reads to PARAMRAM from the slave interface are routed to the register address space.

Figure 1. PARAMRAM vs. CMDRAM
Page-1 Sheet.2 Sheet.3 CMDRAM (RD) CMDRAM (RD) Sheet.4 CMDRAM (WR) CMDRAM (WR) Sheet.5 Sheet.6 Sheet.7 Sheet.8 128-bit 128-bit Sheet.9 0x8000 0x8000 Sheet.10 0x8FFF 0x8FFF Sheet.11 0x9000 0x9000 Sheet.12 0x9FFF 0x9FFF Sheet.13 Sheet.14 PARAMRAM (RD) PARAMRAM (RD) Sheet.15 PARAMRAM (WR) PARAMRAM (WR) Sheet.16 Sheet.17 Sheet.18 Sheet.19 32-bit 32-bit Sheet.20 0x1000 0x1000 Sheet.21 0x13FF 0x13FF Sheet.22 0x1400 0x1400 Sheet.23 0x17FF 0x17FF Sheet.24 Sheet.25 Sheet.26 Sheet.27

Each entry in the PARAMRAM modifies its corresponding CMDRAM entry. The encoding and opcodes are described in the following tables.

Table 1. PARAMRAM Entry Control Signals
Bits Name Description
31:29 Opcode
The opcode defines how the op_control bits are used. Currently, four operations are supported:
Bits Name Description
000 NOP

The command in the CMDRAM executes unaltered.

001 OP_REPEAT

The command in the CMDRAM repeats multiple times.

010 OP_DELAY

The command in the CMDRAM delays before execution.

010 OP_FIXEDREPEAT_DELAY

The command in the CMDRAM repeats multiple times. The repeat count depends on the Vivado IDE option (Repeat Count) provided by you. Delay and address range can be constrained.

28 Idmode Unused
27:26 Intervalmode

Control interval delay validated by OP_FIXEDREPEAT_DELAY.

00 = Constant Delay as programmed with Bits[19:8]

25:24 Addrmode

Control addressing when a command is repeated.

Bits Name Description
00 Constant Address does not change
01 Increment Address increments ((BUSWIDTH / 8) × (AXI_LEN + 1)) between repeated transactions
10 Random Address is randomly generated within a address range. Valid only when OP_FIXEDREPEAT_DELAY is selected.
23:0 PARAMRAM Opcodes The definition for Bits[23:0] depend on the selected PARAMRAM opcodes. The details are described in the following tables.
  1. When using PARAMRAM in Address increment or random address generation mode, ensure that the address specified is aligned to burst boundaries. Failing to do so results in gaps being inserted in the address range. For example, in a 32-bit transaction with 16 being the burst length, the last three bits of the address have to be 0.
  2. All transactions in Random mode are generated with data width aligned addresses.