The PARAMRAM extends the command programmability provided through command RAM by adding
32-bits to the decode of each command. The following figure shows how the PARAMRAM is
addressed in relation to the CMDRAM. Only write access is allowed to the PARAMRAM from
the slave interface. Reads to PARAMRAM from the slave interface are routed to the
register address space.
Figure 1. PARAMRAM vs. CMDRAM
Each entry in the PARAMRAM modifies its corresponding CMDRAM entry. The encoding and
opcodes are described in the following tables.
Table 1. PARAMRAM Entry Control Signals
Bits
Name
Description
31:29
Opcode
The opcode defines how the op_control bits are
used. Currently, four operations are supported:
Bits
Name
Description
000
NOP
The command in the CMDRAM executes
unaltered.
001
OP_REPEAT
The command in the CMDRAM repeats multiple
times.
010
OP_DELAY
The command in the CMDRAM delays before
execution.
010
OP_FIXEDREPEAT_DELAY
The command in the CMDRAM repeats multiple
times. The repeat count depends on the Vivado IDE
option (Repeat Count) provided by you. Delay and
address range can be constrained.
28
Idmode
Unused
27:26
Intervalmode
Control interval delay validated by
OP_FIXEDREPEAT_DELAY.
Address is randomly generated within a
address range. Valid only when
OP_FIXEDREPEAT_DELAY is selected.
23:0
PARAMRAM Opcodes
The definition for Bits[23:0] depend on
the selected PARAMRAM opcodes. The details are described in the
following tables.
When using PARAMRAM in Address increment or
random address generation mode, ensure that the address
specified is aligned to burst boundaries. Failing to do so
results in gaps being inserted in the address range. For
example, in a 32-bit transaction with 16 being the burst length,
the last three bits of the address have to be 0.
All transactions in Random mode are generated
with data width aligned addresses.