Overview - 3.0 English

AXI Traffic Generator LogiCORE IP Product Guide (PG125)

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3.0 English

The AXI Traffic Generator is a fully synthesizable AXI4-compliant core with the following features:

  • Configurable option to generate and accept data according to different traffic profiles
  • Configurable address width for Master AXI4 interface
  • Supports dependent/independent transaction between read/write master port with configurable delays
  • Programmable repeat count for each transaction with constant/increment/random address
  • External start/stop to generate traffic without processor intervention
  • Generates IP-specific traffic on AXI interface for pre-defined protocols
Note: This product guide replaces the LogiCORE IP AXI Exerciser Product Guide (PG094).

The core generates AXI4, AXI4-Lite, or AXI4-Stream traffic based on the mode selected. The AXI Traffic Generator core can be configured in six different modes, as detailed in the following table.

Table 1. AXI Traffic Generator Modes
Mode Traffic Type Description
Advanced AXI4 Supports all AXI4 features.
Basic AXI4 Lightweight mode with basic AXI4 features support (narrow, unaligned, out-of-order transfers are not supported).
Static AXI4 Simple AXI4 traffic generator mode with fixed address, incremental transactions based on UI configuration. Minimum processor overhead.
High Level Traffic AXI4 Generates IP specific traffic on AXI4 interface for pre-defined protocols.
System Init/Test AXI4-Lite AXI4-Lite interface for system initialization or simple system testing. Transactions initiated based on memory initialization files.
Streaming AXI4-Stream AXI4-Stream interface with Master, Slave, and Loopback mode option.

The architecture of the core is broadly separated into a Master and Slave block, and each contains the Write and Read blocks. Other support functions are provided by the Control registers and internal RAMs.

The following figure shows the top-level AXI4 Traffic Generator block diagram.

Figure 1. AXI4 Traffic Generator Block Diagram
LogiCORE IP AXI Traffic Generator Page-1 Sheet.43 Registers Registers Sheet.44 Slave Write/Read Slave Write/Read Sheet.45 Master Write Master Write Sheet.46 Master Read Master Read Sheet.47 MSTRAM MSTRAM Sheet.48 Sheet.49 Sheet.50 Sheet.51 s_axi_aclk s_axi_aclk Sheet.52 Sheet.53 s_axi_aresetn s_axi_aresetn Sheet.54 irq_out irq_out Sheet.55 err_out err_out Sheet.56 S_AXI S_AXI Sheet.57 M_AXI M_AXI Sheet.58 dbg_out dbg_out Sheet.59 dbg_out_ext dbg_out_ext Sheet.60 Sheet.61 PARAMRAM PARAMRAM Sheet.62 CMDRAM CMDRAM Sheet.63 Sheet.64 Sheet.65 Sheet.66 Sheet.67 Sheet.68 Sheet.69 Sheet.70 Sheet.71 Sheet.72 Sheet.73 Sheet.74 Sheet.75 Sheet.76 Sheet.77 Sheet.78 Sheet.79 Sheet.80 Sheet.81 Sheet.82 Sheet.83 Sheet.84 Sheet.85 Sheet.86 Sheet.87 Sheet.88 Sheet.89 Sheet.90 Sheet.91 Sheet.92 Sheet.93 Sheet.94 Sheet.95 Sheet.96 Sheet.97 Sheet.98 Sheet.99 Sheet.100 Sheet.101 Sheet.102 Sheet.103 Sheet.104 Sheet.105 Sheet.106 Sheet.107 Sheet.108 Sheet.109 Sheet.110 Sheet.111 Sheet.112 Sheet.113 Sheet.114 Sheet.115 Sheet.116 Sheet.117 Sheet.118 Sheet.119 Arrow LG Right Arrow Sm Right Arrow Sm Right.56 Arrow Sm Right.57 Arrow Sm Right.58 Sheet.125 MSTRAM ADDRRAM

The following figure shows the top-level AXI4-Lite Traffic Generator block diagram.

Figure 2. AXI4-Lite Traffic Generator Block Diagram
Page-1 Sheet.2 Slave Write/Read RAM Sheet.3 Master Write Write Gen Sheet.4 Master Read Read Gen Sheet.5 MSTRAM Control Logic Sheet.6 Sheet.8 Sheet.9 s_axi_aclk s_axi_aclk Sheet.10 Sheet.11 s_axi_aresetn s_axi_aresetn Sheet.15 M_AXI done Sheet.75 Sheet.77 Arrow LG Right Dynamic connector Sheet.7 Sheet.12 M_AXI status Sheet.13 Sheet.14 M_AXI M_AXI_LITE_CH1 Sheet.16 Sheet.17 M_AXI M_AXI_LITE_CH2 Sheet.18 Sheet.19 M_AXI M_AXI_LITE_CH3 Sheet.20 Sheet.21 M_AXI M_AXI_LITE_CH4 Sheet.22 Sheet.23 M_AXI M_AXI_LITE_CH5

The following figure shows the top-level AXI4-Stream Traffic Generator block diagram.

Figure 3. AXI4-Stream Traffic Generator Block Diagram
Page-1 Box Registers Registers Arrow LG Double Arrow LG Double.3 Box.4 OUT_CH1 OUT_CH1 Box.5 OUT_CH2 OUT_CH2 Box.6 IN_CH2 IN_CH2 Box.7 Str_fifo Str_fifo Box.8 Box.9 Box.10 Arrow LG Double.11 Arrow LG Double.12 Arrow LG Double.13 Arrow LG Double.14 Arrow LG Double.15 Arrow LG Double.16 Text 8pt s_axi_clk s_axi_clk Text 8pt.18 s_axi_reset s_axi_reset Text 8pt.19 AXI4 AXI4 Text 8pt.20 AXIS1_OUT M_AXIS_MASTER2 Text 8pt.21 AXIS2_OUT M_AXIS_SLAVE3 Text 8pt.22 AXIS2_IN S_AXIS_SLAVE3 Arrow LG Double.1 Text 8pt.2 AXIS1_OUT S_AXIS_MASTER1 Box.25 Str_fifo checker Box.26 OUT_CH1 IN_CH1 Sheet.27 Notes: 1. Available in Master Loop Back mode. 2. Available in... Notes:1. Available in Master Loop Back mode.2. Available in Master Only and Master Loop Back modes.3. Available in Slave Loop Back mode.