The AXI Traffic Generator is a fully synthesizable AXI4-compliant core with the following features:
- Configurable option to generate and accept data according to different traffic profiles
- Configurable address width for Master AXI4 interface
- Supports dependent/independent transaction between read/write master port with configurable delays
- Programmable repeat count for each transaction with constant/increment/random address
- External start/stop to generate traffic without processor intervention
- Generates IP-specific traffic on AXI interface for pre-defined protocols
The core generates AXI4, AXI4-Lite, or AXI4-Stream traffic based on the mode selected. The AXI Traffic Generator core can be configured in six different modes, as detailed in the following table.
| Mode | Traffic Type | Description |
|---|---|---|
| Advanced | AXI4 | Supports all AXI4 features. |
| Basic | AXI4 | Lightweight mode with basic AXI4 features support (narrow, unaligned, out-of-order transfers are not supported). |
| Static | AXI4 | Simple AXI4 traffic generator mode with fixed address, incremental transactions based on UI configuration. Minimum processor overhead. |
| High Level Traffic | AXI4 | Generates IP specific traffic on AXI4 interface for pre-defined protocols. |
| System Init/Test | AXI4-Lite | AXI4-Lite interface for system initialization or simple system testing. Transactions initiated based on memory initialization files. |
| Streaming | AXI4-Stream | AXI4-Stream interface with Master, Slave, and Loopback mode option. |
The architecture of the core is broadly separated into a Master and Slave block, and each contains the Write and Read blocks. Other support functions are provided by the Control registers and internal RAMs.
The following figure shows the top-level AXI4 Traffic Generator block diagram.
The following figure shows the top-level AXI4-Lite Traffic Generator block diagram.
The following figure shows the top-level AXI4-Stream Traffic Generator block diagram.