Throughput is measured on the master write channel for transaction with Length = 255 (Maximum burst length) for a 32-bit data bus width.
Throughput = (A – B) × 100 / (Total beats in
the transaction)
A = Number of clock cycles wvalid and
wready are asserted = 256
B = Number of clock cycles wvalid is
deasserted, wready is asserted = 0
Throughput = (256 – 0) × 100 / 256 =
100%
Figure 1. Master Write Channel Throughput
