The MSTRAM has 8 KB of internal RAM used for the following:
- Take data from this RAM for write transactions
- Store data to this RAM for read transaction
The RAM address to use for a read/write transaction is controlled through command RAM programming.
The Master RAM A and B channels are shown connected in the following figure.
MSTRAM Index defines where to take data from MSTRAM (in case of write) and where to store the data (in case of read) in Advanced/Basic mode of operation. The following table shows details for the write data.
Address | Data | MSTRAM Entry Number (Index Entered in CMDRAM Programming) |
---|---|---|
0xC000 | 0x11111111 | 0 |
0xC004 | 0x22222222 | |
0xC008 | 0x33333333 | 1 |
0xC00C | 0x44444444 | |
0xC010 | 0xABCD1234 | 2 |
0xC014 | 0xFAAB1234 | |
… |
In the case of Read, the Index definition changes based on the data width of the AXI4 Master interface. The following table shows details for data widths ≤ 64.
Address | Data | MSTRAM Entry Number (Index Entered in CMDRAM Programming) |
---|---|---|
0xC000 | 0x11111111 | 0 |
0xC004 | 0x22222222 | |
0xC008 | 0x33333333 | 1 |
0xC00C | 0x44444444 | |
0xC010 | 0xABCD1234 | 2 |
0xC014 | 0xFAAB1234 | |
… |
For data width > 64, rdata is stored at the 128/256/512 aligned locations (mstram_index should be set in the same manner).
AXI data width = 128-bit (mstram_index valid values =
0x0
, 0x10
, 0x20
,
0x30
, 0x40
,…)
Example:
mstram_index = 0x10
First Incoming data beat (lsb2msb) = 0xAABBCCDD_00112233_44556677_88888888
Second Incoming data beat (lsb2msb) = 0xFFEEDDCC_55555555_44556677_88888888
Address | Data |
---|---|
0x0 | 000000000 |
0x | 000000000 |
0x | 000000000 |
0x | 000000000 |
0x10 | AABBCCDD |
0x | 00112233 |
0x | 000000000 |
0x | 000000000 |
0x20 | FFEEDDCC |
0x | 55555555 |
0x | 000000000 |
0x | 000000000 |
0x30 | : |
0x | : |
0x | 000000000 |
AXI data width = 256-bit (mstram_index valid values =
0x0
, 0x20
, 0x40
…)
Example:
mstram_index = 0x20
First Incoming data beat (lsb2msb) =
0xAABBCCDD_00112233_44556677_88888888_55665566_22113344_AAAAAAAA_FFFFFFFF
Second Incoming data beat (lsb2msb) =
0xFFEEDDCC_55555555_44556677_88888888_55665566_22113344_AAAAAAAA_FFFFFFFF
Address | Data |
---|---|
0x0 | 000000000 |
0x | 000000000 |
0x | 000000000 |
0x | 000000000 |
0x | 000000000 |
0x | 000000000 |
0x | 000000000 |
0x | 000000000 |
0x20 | AABBCCDD |
0x | 00112233 |
0x | 000000000 |
0x | 000000000 |
0x | 000000000 |
0x | 000000000 |
0x | 000000000 |
0x | 000000000 |
0x40 | FFEEDDCC |
0x | 55555555 |
0x | 000000000 |
0x | 000000000 |
0x | 000000000 |
0x | 000000000 |
0x | 000000000 |
0x | 000000000 |
0x60 | : |
0x | : |