Master Error Interrupt Enable register enables interrupt generation for AXI4 Master interface based on the Error Status register.
| Bits | Name | Reset Value | Access Type | Description |
|---|---|---|---|---|
| 31:16 | Reserved | N/A | N/A | Reserved |
| 15 | MINTREN | 0x0 | R/W |
Enables Master Interrupt When set, if any bit in Error Status register Bits[30:16] is set, then err_out is asserted. |
| 14:0 | Reserved | N/A | N/A | Reserved |