Master Control register allows you to configure the master interface ID width and control to enable the AXI traffic.
Bits | Name | Reset Value | Access Type | Description |
---|---|---|---|---|
31:24 | REV | 0x20 | R | Revision of the core. |
23:21 | MSTID | 0x0 | R |
M_ID_WIDTH, where: 0x0 = Indicates 0 or 1-bit width 0x1 = Indicates 2-bit width ... 0x7 = Indicates 8-bit width |
20 | MSTEN | 0x0 | R/W |
Master Enable When set, the master logic begins. When both the Read and Write state machines complete, this bit is automatically cleared to indicate to the software that the AXI Traffic Generator is done. |
19 | Loop Enable 1 | 0x0 | R/W |
Loop Enable
Note: Dependency for the last command set run
is based on the point at which the loop enable is reset to 0.
For example, a command set with 12 writes and 16 reads is
present with the 13th read is dependent on the sixth
write. Now if the loop enable is reset to 0 before the sixth
write and 13th read of command run, you see the
dependency in the last run else the dependency is not seen even
after loop enable is reset.
For bullet point 4, consider a case of a command set with 50 write commands and two read commands. In such a case, the read command should be repeated more than once before one set of write commands is completed. |
18:0 | Reserved | N/A | N/A | Reserved |
|