For writes, each CMD is read from the CMDRAM and pushed to the 2-deep Maw_fifo and
Maw_fifow. Maw_fifo is connected to the AXI_M AW
signals and drives the
request to the switch. Maw_fifow holds two requests heading to the Maw_agen block which
generates addresses into the MSTRAM. Data read from MSTRAM is pushed into the Mw_fifo,
which is connected to the AXI_M W
signals.
To return BRESP out of order, Maw_agen feeds into Maw_track which tracks up to four IDs in a similar way to Mar_track. A write ID is assigned to an Mw_fifo0 to 3. When that ID receives a BRESP, it pops the corresponding Mw_fifo0 to 3. This allows the master write logic to handle receiving BRESPs out of order.