IP Facts - 3.0 English

AXI Traffic Generator LogiCORE IP Product Guide (PG125)

Document ID
PG125
Release Date
2023-10-18
Version
3.0 English
AMD LogiCORE™ IP Facts Table
Core Specifics
Supported Device Family 1 AMD UltraScale+™ Families, AMD UltraScale™ Architecture, AMD Zynq™ 7000 SoC, 7 series FPGAs
Supported User Interfaces AXI4, AXI4-Lite, AXI4-Stream
Resources Performance and Resource Utilization web page
Provided with Core
Design Files Verilog
Example Design Verilog
Test Bench Verilog
Constraints File Xilinx Design Constraints (XDC)
Simulation Model Not Provided
Supported S/W Driver 2 Standalone and Linux
Tested Design Flows 3
Design Entry AMD Vivado™ Design Suite
Simulation For supported simulators, see the Vivado Design Suite User Guide: Release Notes, Installation, and Licensing (UG973).
Synthesis Vivado Synthesis
Support
Release Notes and Known Issues Master Answer Record: 54426
All Vivado IP Change Logs Master Vivado IP Change Logs: 72775
Support web page
  1. For a complete list of supported devices, see the AMD Vivado™ IP catalog.
  2. Standalone driver details can be found in <install_directory>/Vitis/<release>/data/embeddedsw/doc/xilinx_drivers_api_toc.htm.

  3. For the supported versions of third-party tools, see the Vivado Design Suite User Guide: Release Notes, Installation, and Licensing (UG973).