General Checks - 3.0 English - PG125

Ensure that all the timing constraints for the core were properly incorporated from the example design and that all constraints were met during implementation.

• Does it work in post-place and route timing simulation? If problems are seen in hardware but not in timing simulation, this could indicate a PCB issue. Ensure that all clock sources are active and clean.
• If using MMCMs in the design, ensure that all MMCMs have obtained lock by monitoring the locked port.
• If your outputs go to 0, check your licensing.
• If the core is not generating any transactions on Write/Read master interfaces:
  1. Ensure valid_cmd bits are set properly while loading commands to command RAM.
  2. Check My_depend, Other depend fields are set correctly so as not to cause a dead-lock situation.
  3. Check delay values programmed to PARAMRAM and wait for sufficient time for the core to insert these delays while generating the transactions.
• If the register control bit (reg0_m_enable) is not getting deasserted:
  1. Ensure valid_cmd bits are set properly while loading commands to command RAM.
  2. Check if Reg0_master_control [18:0] is set to 0.
  3. Check delay values programmed to PARAMRAM and wait for sufficient time for the core to insert these delays while generating the transactions.
• In Streaming mode, the core is generating a random length of transactions instead of the programed length.
  1. Ensure RANLEN is set to 0 in the Streaming Config register before enabling the core.