Features - 3.0 English

AXI Traffic Generator LogiCORE IP Product Guide (PG125)

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3.0 English
  • AXI4 interface for register access and data transfers.
  • Multi-Mode operation (AXI4 Master, AXI4-Lite Master, and AXI4-Stream Master).
  • Flexible data width capability (32/64-bit) on output AXI4 Slave, (32/64/128/256/512-bit) on output AXI4 Master interface.
  • Flexible address width capability from 32 to 64-bit on AXI4 Master Interface.
  • Flexible data width capability from 8-bit to 1,024-bit in multiples of eight output AXI4-Stream Master/Slave interface.
  • Supports AXI4-Lite Master interface for system initialization in processor-less system.
  • Interrupt support for indicating completion for traffic generation.
  • Error interrupt pin indicating error occurred during core operation. Error registers can be read to understand the error occurred. Only supported in Advanced mode.
  • Initialization support through Memory initialization files to internal RAM (CMDRAM, PARAMRAM, and MSTRAM) allows you to initialize the contents of all RAMs for a desired traffic profile.
  • External global start/stop to synchronize multiple AXI Traffic Generators in the system and to enable AXI Traffic Generator without processor intervention.
  • Supports high level traffic generation for different traffic profiles.