Error Status register reports the errors that occurred during the operation of the AXI Traffic Generator core.
| Bits | Name | Reset Value | Access Type | Description |
|---|---|---|---|---|
| 31 | MSTDONE | 0x0 | R/W1C |
Master Completion Set when both master write and master read CMD logic completes and Error Enable register Bit[31] is 1. When set, irq_out is driven to 1. |
| 30:21 | Reserved | N/A | N/A | Reserved |
| 20 | RIDER | 0x0 | R/W1C |
Master Read ID Error On master interface Received an RVALID with a RID that did not match any pending reads. |
| 19 | WIDER | 0x0 | R/W1C |
Master Write ID Error Received a BVALID with a BID that did not match any pending writes. |
| 18 | WRSPER | N/A | R/W1C |
Master Write Response Error On a master write completion, the response returned was not allowed by expected_resp[2:0]. |
| 17 | RERRSP | 0x0 | R/W1C |
Master Read Response Error On a master read completion, the response returned was not allowed by expected_resp[2:0]. |
| 16 | RLENER | 0x0 | R/W1C |
Master Read Length Error On the master interface Rlast either when it was not expected or was not signaled when it was expected. |
| 15:2 | Reserved | N/A | N/A | Reserved |
| 1 | SWSTRB | 0x0 | R/W1C |
Slave Write Strobe Error On the slave interface, a WSTRB assertion was detected on an illegal byte lane. |
| 0 | SWLENER | 0x0 | R/W1C |
Slave Write Length Error On the slave interface W, Last was signaled either when it was not expected or was not signaled when it was expected. |
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