Error Enable - 3.0 English - PG125

AXI Traffic Generator LogiCORE IP Product Guide (PG125)
Document ID
PG125
Release Date
2023-10-18
Version
3.0 English

Error Enable register allows you to enable the particular error condition in the AXI Traffic Generator. If an error occurs but the corresponding bit in the Error Enable register is not set, then the bit in the Error Status register is not set and no error signaling occurs. To enable all errors, set the Error Enable register to 0xFFFF_FFFF.

This enables/disables error reporting on the Error Status register.

Table 1. Error Enable (0x0C)
Bits Name Reset Value Access Type Description
31 MSTIRQEN 0x1 R/W Enables interrupt generation for Master transfer completion.
30:21 Reserved N/A N/A Reserved
20 RIDEREN 0x0 R/W Enables Read ID Error for Error Status register Bit[20].
19 WIDEREN 0x0 R/W Enables Write ID error for Error Status register Bit[19].
18 WRSPER N/A R/W Enables write response error for Error Status register Bit[18].
17 RERRSP 0x0 R/W Enables read response error for Error Status register Bit[17].
16 RLENER 0x0 R/W Enables read length error for Error Status register Bit[16].
15:2 Reserved N/A N/A Reserved
1 SWSTRBEN 0x0 R/W Enables slave write strobe error for Error Status register Bit[1].
0 SWLENEREN 0x0 R/W Enables slave write length error for Error Status register Bit[0].