This section contains information about constraining the core in the Vivado Design Suite. There are no IP-specific constraints other than the AXI clock constraint and the necessary constraints delivered when IP is generated. This core generates the out-of-context (OOC) XDCs.
Required Constraints
This section is not applicable for this IP core.
Device, Package, and Speed Grade Selections
This section is not applicable for this IP core.
Clock Frequencies
This section is not applicable for this IP core.
Clock Management
This section is not applicable for this IP core.
Clock Placement
This section is not applicable for this IP core.
Banking
This section is not applicable for this IP core.
Transceiver Placement
This section is not applicable for this IP core.
I/O Standard and Placement
This section is not applicable for this IP core.