Command RAM - 3.0 English

AXI Traffic Generator LogiCORE IP Product Guide (PG125)

Document ID
PG125
Release Date
2023-10-18
Version
3.0 English

The CMDRAM is divided into two 4 KB regions, one for reads and one for writes. Each region of CMDRAM can hold 256 commands. Read and write commands are executed simultaneously and independently. CMDRAM is realized using the dual-port block RAM. Access to CMDRAM is prohibited after the master logic of the core is enabled (Bit[20] MSTEN of Master Control).

Reads are issued to the master-read block AR channel from CMDRAM (0x000 to 0xFFF) locations (up to 256 commands of 128-bits each). Writes are issued to the master-write block AW channel from CMDRAM (0x1000 to 0x1FFF ) locations (up to 256 commands of 128 bits each). Each command does not indicate whether it is a read or a write because it is implied by its position in the CMDRAM.