CMD Memory Format - 3.0 English

AXI Traffic Generator LogiCORE IP Product Guide (PG125)

Document ID
PG125
Release Date
2023-10-18
Version
3.0 English

Each CMDRAM command in the following table is 128-bits wide.

Table 1. CMDRAM Memory Format
Word Offset Bits Description
+00 31:0 AXI_Address[31:0]: Address to drive on ar_addr or aw_addr (a*_addr[31:0])
+01 31 Valid_cmd 1 : When set, this is a valid command. When clear, halt the master logic for this request type (read or write).
30:28

last_addr[2:0]: Should be set to 0 for C_M_AXI_DATA_WIDTH > 64. For writes, indicates the valid bytes in the last data cycle.

64-bit mode:

000 = All bytes valid

001 = Only Byte 0 is valid

010 = Only Bytes 0 and 1 are valid

...

32-bit mode:

000 = All bytes valid

100 = Only Byte 0 is valid

101 = Only Bytes 0 and 1 are valid

110 = Only Bytes 0, 1, and 2 are valid

27:24 Reserved
23:21 Prot[2:0]: Driven to a*_prot[2:0]
20:15 Id[5:0]: Driven to a*_id[5:0]
14:12 Size[2:0]: Driven to a*_size[2:0]
11:10 Burst[1:0] : Driven to a*_burst[1:0]
9 Reserved
8 Lock: Driven to a*_lock
7:0 Len[7:0]: Driven to a*_len[7:0].
+02 31 Reserved
30:22 My_depend[8:0]: This command does not begin until this master logic has at least completed up to this command number. A value of zero in this field means do not wait. This allows a command to wait until previous commands have completed for ordering.
21:13

Other_depend[8:0]: This command does not begin until the other master logic has completed up to this command number. For example, if a write command had 0x04 in this field, the write would not begin until the read logic had at least completed its commands (CMDs) 0x00 through 0x03.

A value of 0 in this field means do not wait, but commands can only be started in order for each master type. For example, if Write CMD[0x05] waits for Read 0x03, then Write CMD[0x06] cannot start until Read 0x03 completes as well. A read completes when it receives the last cycle of data, and a write completes when it receives BRESP.

12:0 Mstram_index[12:0] 2 : Index into MSTRAM for this transaction (reads will write to this MSTRAM address, writes take data from this address)
+03 31:20 Reserved
19:16 qos[3:0]: Driven to a*_qos[3:0]
15:8 user[7:0]: Driven to a*_user[7:0]
7:4 cache[3:0]: Driven to a*_cache[3:0]
3 Reserved
2:0

Expected_resp:

0x0 to 0x1 = Only OKAY is allowed

0x2 = Only EX_OK is allowed

0x3 = EX_OK or OKAY is allowed

0x4 = Only DECERR or SLVERR is allowed

0x7 = Any response is allowed

  1. Valid_cmd: There should be at least one command with valid_cmd bit set to zero (that is, one invalid command) for both reads and writes.
  2. Mstram_index: MSTRAM is shared by both Read/Write master logic. To avoid memory collision issues, ensure no write command data overlaps with read-command data by selecting proper index values. The MSTRAM index should be aligned the same as the master (Read/Write) address. For example, For a 64-bit aligned transaction, the least three bits should be zero. For a 128-bit aligned transaction, the least four bits should be zero. Address generation for MSTRAM is based on the burst type selected for the command.
  3. It is recommended to write 0s to the command RAM reserved bits.
  4. Address and burst length should be selected such that the transaction does not cross the 4K boundary.
  5. Reads to CMDRAM from slave interface should be burst length 0.