Address RAM - 3.0 English

AXI Traffic Generator LogiCORE IP Product Guide (PG125)

Document ID
PG125
Release Date
2023-10-18
Version
3.0 English

When the address width is configured in Vivado IDE is > 32, the extended address capability for the Master AXI4 interface in the AXI4 mode is available. In cases when address width is configured to 32, the Address RAM is not present and cannot be accessed.

The Address RAM entries correspond to the MSB bits of address and are concatenated to Bits[31:0] in CMDRAM. All 32-bits of RAM are accessible when the address width is > 32, but only the appropriate bits are considered and driven on the m_axi_*addr pins.

For example, if the address width is configured to be 36 in the Vivado IDE, enter a 32-bit value in the Address RAM such as 0x12345678. The 8 is concatenated to address bits in the CMDRAM and are driven on the address lines in the Master AXI4 interface.

Figure 1. Address RAM
LogiCORE IP AXI Traffic Generator Page-1 Sheet.1 Sheet.2 ADDRRAM (RD) ADDRRAM (RD) Sheet.4 Sheet.5 Sheet.6 Sheet.7 32-bit 32-bit Sheet.8 0xA000 0xA000 Sheet.9 0xA3FF 0xA3FF Sheet.10 0xA400 0xA400 Sheet.11 0xA7FF 0xA7FF Sheet.12 ADDRRAM (WR) ADDRRAM (WR) Sheet.3 Sheet.13 Sheet.14 Sheet.15