Address Generation - 3.0 English - PG125

The address generation to the MSTRAM from each of the mentioned block is through the addrgen block. Addrgen blocks receive input for the address information, length, and bus size. Then, it generates output for the an index into the MSTRAM for each beat of the transfer. It also tracks the transfer length and signals to other logic when a transfer is complete.

Addrgen block considers the mstram_index and AXI_Address in the Command RAM entries to generate the MSTRAM address.

Mstram_index should be selected in such a way that it matches AXI_Address offset. The following examples illustrate the mstram_index selection:

32-bit Aligned Transfer

Lower Bits[1:0] of AXI_Address are zero. Mstram_index should also be selected in such a way that the lower Bits[1:0] are zero.

Example:

AXI_Address = 0xC000_0004

Mstram_index = 0x0000_C004

32-bit Unaligned Transfer

Lower Bits[1:0] of AXI_Address are offset by the byte from which transfer should start. Mstram_index should also be selected in such a way that the lower Bits[1:0] are offset by the same byte offset as indicated by AXI_Address.

Example:

AXI_Address = 0xC000_0005 (offset by 1-byte)

Mstram_index = 0x0000_C005 (offset by 1-byte)

64-bit Aligned Transfer

Lower Bits[2:0] of AXI_Address are zero. Mstram_index should also be selected in such a way that the lower Bits[2:0] are zero.

Example:

AXI_Address = 0xC000_0008

Mstram_index = 0x0000_C008

64-bit Unaligned Transfer

Lower Bits[2:0] of AXI_Address are offset by the byte from which transfer should start. Mstram_index should also be selected in such a way that the lower Bits[2:0] are offset by the same byte offset as indicated by AXI_Address.

Example:

AXI_Address = 0xC000_0005 (offset by 5 bytes)

Mstram_index = 0x0000_C005 (offset by 5 bytes)

Similar rules apply for higher data width (128/256/512) transactions. Only aligned transfers are supported for 128/256/512-bit width selection.