AXI4 Interfaces - 3.0 English

AXI Traffic Generator LogiCORE IP Product Guide (PG125)

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3.0 English

Read from a register that does not have all 0s (for example, Reg0_master_control ) as a default to verify that the interface is functional. See the following figure for a read timing diagram. Output s_axi_arready asserts when the read address is valid, and output s_axi_rvalid asserts when the read data/response is valid. If the interface is unresponsive, ensure that the following conditions are met:

  • The s_axi_aclk input is connected and toggling.
  • The interface is not being held in reset, and s_axis_aresetn is an active-Low reset.
  • The main core clocks are toggling and the enables are also asserted.
  • If the simulation has been run, verify in simulation and/or a Vivado Design Suite debug feature capture that the waveform is correct for accessing the AXI4 interface.
Figure 1. AXI4 Read Timing Diagram