The CHI master interface is compliant to Arm AMBA-5 CHI Architecture Specification, Arm IHI0050B. The following features are supported:
- One Request Node (RN-F)
- Data width 512 bits
- Address width 48 bits
- 64 byte cache line
- All available sizes are supported for Read and Write requests
- The following transactions are generated under normal conditions:
-
ReadNoSnp,ReadOnce,ReadUnique,ReadShared,CleanShared,CleanUnique,CleanInvalid,MakeInvalid,WriteNoSnp,WriteUnique,WriteBackFullSD,WriteBackFullUD
-
- The following transactions can be generated when atomic transactions
are enabled:
-
AtomicStore_ADD,AtomicStore_CLR,AtomicStore_EOR,AtomicStore_SET,AtomicStore_SMAX,AtomicStore_SMIN,AtomicStore_UMAX,AtomicStore_UMIN,AtomicLoad_ADD,AtomicLoad_CLR,Atomicoad_EOR,AtomicLoad_SET,AtomicLoad_SMAX,AtomicLoad_SMIN,AtomicLoad_UMAX,AtomicLoad_UMIN,AtomicSwap,AtomicCompare
-
- All normal and forward snoop combinations