This system represents a typical use case where it is required to monitor an error frequency, as well as generating an interrupt to immediately correct a single bit error through software. It does not provide support for testing the ECC function.
This is a small system with the addition of Correctable Error First Failing registers and a Status register. A single bit error latches the address for the access into the Correctable Error First Failing Address Register and sets the CE_STATUS bit in the ECC Status Register. An interrupt is generated, triggering MicroBlaze to read the failing address and then perform a read followed by a write on the failing address. This removes the single bit error from the on-chip RAM. Thus, it reduces the risk of the single bit error becoming an uncorrectable double bit error. Parameters set are C_ECC = 1, C_CE_COUNTER_WIDTH = 10, C_ECC_STATUS_REGISTER = 1, and C_CE_FAILING_REGISTERS = 1.