Throughput - Throughput - 4.0 English - PG112

LMB Block RAM Interface Controller LogiCORE IP Product Guide (PG112)

Document ID
PG112
Release Date
2025-11-20
Version
4.0 English

The nominal throughput is one read or write access every clock cycle. The only exceptions are performing a byte or half word write when ECC is enabled with 32-bit data width, performing a word write when ECC is enabled with 64-bit data width, and when an access is ongoing on another port with the use of multiple ports simultaneously.