Revision History - Revision History - 4.0 English - PG112

LMB Block RAM Interface Controller LogiCORE IP Product Guide (PG112)
Document ID
PG112
Release Date
2025-11-20
Version
4.0 English

The following table shows the revision history for this document.

Section Revision Summary
11/20/2025 Version 4.0
Entire doc Updated with description of LMB protection feature.
05/17/2023 Version 4.0
N/A
  • Added four additional LMB slave interfaces
  • Added information about round-robin arbitration support for the LMB slave interfaces
  • Described 64-bit data width
01/21/2021 Version 4.0
N/A
  • Added Versal Adaptive SoC support
  • Added URAM use information
  • Clarified that reported first failing address is a word address
  • Describe behavior for instruction prefetch
11/14/2018 Version 4.0
N/A
  • Updated register descriptions to use AXI bit order, with bit 0 as least significant bit.
  • Added reference to additional information on the software driver.
12/20/2017 Version 4.0
N/A Corrected Fault Injection ECC register description.
10/04/2017 Version 4.0
N/A Added support for First Failing Address register with extended addressing.
04/06/2016 Version 4.0
N/A Updated with description of extended addressing.
11/18/2015 Version 4.0
N/A Added support for UltraScale+ families.
06/24/2015 Version 4.0
N/A Moved performance and resource utilization data to the web.
03/20/2013 Version 1.0
N/A This Product Guide replaces PG061. There are no documentation changes for this release.