The following table shows the Register Address Map for the LMB Block RAM Interface Controller. The individual registers are described in Table 1 to Table 1 .
| Offset (hex) | Register | Access Type | Description |
|---|---|---|---|
| 0x0 | ECC_STATUS | R/W | ECC Status Register |
| 0x4 | ECC_EN_IRQ | R/W | ECC Enable Interrupt Register |
| 0x8 | ECC_ONOFF | R/W | ECC On/Off Register |
| 0xC | CE_CNT | R/W | Correctable Error Counter Register |
| 0x100-0x104 | CE_FFD | R | Correctable Error First Failing Data Register |
| 0x180 | CE_FFE | R | Correctable Error First Failing ECC Register |
| 0x1C0-0x1C4 | CE_FFA | R | Correctable Error First Failing Address Register |
| 0x200-0x204 | UE_FFD | R | Uncorrectable Error First Failing Data Register |
| 0x280 | UE_FFE | R | Uncorrectable Error First Failing ECC Register |
| 0x2C0-0x2C4 | UE_FFA | R | Uncorrectable Error First Failing Address Register |
| 0x300-0x304 | FI_D | W | Fault Inject Data Register |
| 0x380 | FI_ECC | W | Fault Inject ECC Register |