The I/O ports and signals for the LMB Block RAM Interface Controller are listed and described in the following table.
| Port Name | MSB:LSB | I/O | Description |
|---|---|---|---|
| LMB Signals | |||
| LMB_Clk | NA | I | LMB Clock |
| LMB_Rst | NA | I | LMB Reset (Active-High) |
| LMB_Prot | 0:1 | I | LMB Protection |
| LMB_ABus | 0:C_LMB_AWIDTH-1 | I | LMB Address Bus |
| LMB_WriteDBus | 0:C_LMB_DWIDTH-1 | I | LMB Write Data Bus |
| LMB_ReadStrobe | NA | I | LMB Read Strobe |
| LMB_AddrStrobe | NA | I | LMB Address Strobe |
| LMB_WriteStrobe | NA | I | LMB Write Strobe |
| LMB_BE | 0:C_LMB_DWIDTH/8-1 | I | LMB Byte Enable Bus |
| Sl_DBus | 0:C_LMB_DWIDTH-1 | O | LMB Read Data Bus |
| Sl_Ready | NA | O | LMB Data Ready |
| Sl_Wait | NA | O | LMB Wait |
| Sl_CE | NA | O | LMB Correctable Error |
| Sl_UE | NA | O | LMB Uncorrectable or Protection Error |
| LMB1_ABus | 0:C_LMB_AWIDTH-1 | I | LMB1 Address Bus |
| LMB1_Prot | 0:1 | I | LMB1 Protection |
| LMB1_WriteDBus | 0:C_LMB_DWIDTH-1 | I | LMB1 Write Data Bus |
| LMB1_ReadStrobe | NA | I | LMB1Read Strobe |
| LMB1_AddrStrobe | NA | I | LMB1 Address Strobe |
| LMB1_WriteStrobe | NA | I | LMB1 Write Strobe |
| LMB1_BE | 0:C_LMB_DWIDTH/8-1 | I | LMB1 Byte Enable Bus |
| Sl1_DBus | 0:C_LMB_DWIDTH-1 | O | LMB1 Read Data Bus |
| Sl1_Ready | NA | O | LMB1 Data Ready |
| Sl1_Wait | NA | O | LMB1 Wait |
| Sl1_CE | NA | O | LMB1 Correctable Error |
| Sl1_UE | NA | O | LMB1 Uncorrectable or Protection Error |
| LMB2_ABus | 0:C_LMB_AWIDTH-1 | I | LMB2 Address Bus |
| LMB2_Prot | 0:1 | I | LMB2 Protection |
| LMB2_WriteDBus | 0:C_LMB_DWIDTH-1 | I | LMB2 Write Data Bus |
| LMB2_ReadStrobe | NA | I | LMB2 Read Strobe |
| LMB2_AddrStrobe | NA | I | LMB2 Address Strobe |
| LMB2_WriteStrobe | NA | I | LMB2 Write Strobe |
| LMB2_BE | 0:C_LMB_DWIDTH/8-1 | I | LMB2 Byte Enable Bus |
| Sl2_DBus | 0:C_LMB_DWIDTH-1 | O | LMB2 Read Data Bus |
| Sl2_Ready | NA | O | LMB2 Data Ready |
| Sl2_Wait | NA | O | LMB2 Wait |
| Sl2_CE | NA | O | LMB2 Correctable Error |
| Sl2_UE | NA | O | LMB2 Uncorrectable or Protection Error |
| LMB3_ABus | 0:C_LMB_AWIDTH-1 | I | LMB3 Address Bus |
| LMB3_Prot | 0:1 | I | LMB3 Protection |
| LMB3_WriteDBus | 0:C_LMB_DWIDTH-1 | I | LMB3 Write Data Bus |
| LMB3_ReadStrobe | NA | I | LMB3 Read Strobe |
| LMB3_AddrStrobe | NA | I | LMB3 Address Strobe |
| LMB3_WriteStrobe | NA | I | LMB3 Write Strobe |
| LMB3_BE | 0:C_LMB_DWIDTH/8-1 | I | LMB3 Byte Enable Bus |
| Sl3_DBus | 0:C_LMB_DWIDTH-1 | O | LMB3 Read Data Bus |
| Sl3_Ready | NA | O | LMB3 Data Ready |
| Sl3_Wait | NA | O | LMB3 Wait |
| Sl3_CE | NA | O | LMB3 Correctable Error |
| Sl3_UE | NA | O | LMB3 Uncorrectable or Protection Error |
| LMB4_ABus | 0:C_LMB_AWIDTH-1 | I | LMB4 Address Bus |
| LMB4_Prot | 0:1 | I | LMB4 Protection |
| LMB4_WriteDBus | 0:C_LMB_DWIDTH-1 | I | LMB4 Write Data Bus |
| LMB4_ReadStrobe | NA | I | LMB4 Read Strobe |
| LMB4_AddrStrobe | NA | I | LMB4 Address Strobe |
| LMB4_WriteStrobe | NA | I | LMB4 Write Strobe |
| LMB4_BE | 0:C_LMB_DWIDTH/8-1 | I | LMB4 Byte Enable Bus |
| Sl4_DBus | 0:C_LMB_DWIDTH-1 | O | LMB4 Read Data Bus |
| Sl4_Ready | NA | O | LMB4 Data Ready |
| Sl4_Wait | NA | O | LMB4 Wait |
| Sl4_CE | NA | O | LMB4 Correctable Error |
| Sl4_UE | NA | O | LMB4 Uncorrectable or Protection Error |
| LMB5_ABus | 0:C_LMB_AWIDTH-1 | I | LMB5 Address Bus |
| LMB5_Prot | 0:1 | I | LMB5 Protection |
| LMB5_WriteDBus | 0:C_LMB_DWIDTH-1 | I | LMB5 Write Data Bus |
| LMB5_ReadStrobe | NA | I | LMB5 Read Strobe |
| LMB5_AddrStrobe | NA | I | LMB5 Address Strobe |
| LMB5_WriteStrobe | NA | I | LMB5 Write Strobe |
| LMB5_BE | 0:C_LMB_DWIDTH/8-1 | I | LMB5 Byte Enable Bus |
| Sl5_DBus | 0:C_LMB_DWIDTH-1 | O | LMB5 Read Data Bus |
| Sl5_Ready | NA | O | LMB5 Data Ready |
| Sl5_Wait | NA | O | LMB5 Wait |
| Sl5_CE | NA | O | LMB5 Correctable Error |
| Sl5_UE | NA | O | LMB5 Uncorrectable or Protection Error |
| LMB6_ABus | 0:C_LMB_AWIDTH-1 | I | LMB6 Address Bus |
| LMB6_Prot | 0:1 | I | LMB6 Protection |
| LMB6_WriteDBus | 0:C_LMB_DWIDTH-1 | I | LMB6 Write Data Bus |
| LMB6_ReadStrobe | NA | I | LMB6 Read Strobe |
| LMB6_AddrStrobe | NA | I | LMB6 Address Strobe |
| LMB6_WriteStrobe | NA | I | LMB6 Write Strobe |
| LMB6_BE | 0:C_LMB_DWIDTH/8-1 | I | LMB6 Byte Enable Bus |
| Sl6_DBus | 0:C_LMB_DWIDTH-1 | O | LMB6 Read Data Bus |
| Sl6_Ready | NA | O | LMB6 Data Ready |
| Sl6_Wait | NA | O | LMB6 Wait |
| Sl6_CE | NA | O | LMB6 Correctable Error |
| Sl6_UE | NA | O | LMB6 Uncorrectable or Protection Error |
| LMB7_ABus | 0:C_LMB_AWIDTH-1 | I | LMB7 Address Bus |
| LMB7_Prot | 0:1 | I | LMB7 Protection |
| LMB7_WriteDBus | 0:C_LMB_DWIDTH-1 | I | LMB7 Write Data Bus |
| LMB7_ReadStrobe | NA | I | LMB7 Read Strobe |
| LMB7_AddrStrobe | NA | I | LMB7 Address Strobe |
| LMB7_WriteStrobe | NA | I | LMB7 Write Strobe |
| LMB7_BE | 0:C_LMB_DWIDTH/8-1 | I | LMB7 Byte Enable Bus |
| Sl7_DBus | 0:C_LMB_DWIDTH-1 | O | LMB7 Read Data Bus |
| Sl7_Ready | NA | O | LMB7 Data Ready |
| Sl7_Wait | NA | O | LMB7 Wait |
| Sl7_CE | NA | O | LMB7 Correctable Error |
| Sl7_UE | NA | O | LMB7 Uncorrectable or Protection Error |
| On-Chip RAM Interface Signals (Data and ECC) | |||
| BRAM_Rst_A | NA | O | Block RAM Reset |
| BRAM_Clk_A | NA | O | Block RAM Clock |
| BRAM_EN_A | NA | O | Block RAM Enable |
| BRAM_WEN_A | 0:(C_LMB_DWIDTH+8*C_ECC)/8-1 | O | Block RAM Write Enable |
| BRAM_Addr_A | 0:C_BRAM_AWIDTH-1 | O | Block RAM Address |
| BRAM_Din_A | 0:C_LMB_DWIDTH+8*C_ECC-1 | I | Block RAM Data Input |
| BRAM_Dout_A | 0:C_LMB_DWIDTH+8*C_ECC-1 | O | Block RAM Data Output |
| Miscellaneous Signals | |||
| Interrupt | NA | O | Interrupt |
| UE | NA | O | One cycle pulse signalling an ECC Uncorrectable Data Error or Protection Error |
| CE | NA | O | One cycle pulse signalling an ECC Correctable Data Error |
| AXI System Signals | |||
| S_AXI_CTRL_ACLK | NA | I | AXI Clock |
| S_AXI_CTRL_ARESETN | NA | I | AXI Reset, active-Low |
| AXI Write Address Channel Signals | |||
| S_AXI_CTRL_AWADDR | C_S_AXI_CTRL_ADDR_WIDTH-1:0 | I | AXI Write address. The write address bus gives the address of the write transaction. |
| S_AXI_CTRL_AWVALID | NA | I | Write address valid. This signal indicates that valid write address is available. |
| S_AXI_CTRL_AWREADY | NA | O | Write address ready. This signal indicates that the slave is ready to accept an address. |
| AXI Write Channel Signals | |||
| S_AXI_CTRL_WDATA | C_S_AXI_CTRL_DATA_WIDTH-1: 0 | I | Write data |
| S_AXI_CTRL_WSTB | C_S_AXI_CTRL_DATA_WIDTH/8-1:0 | I | Write strobes. This signal indicates which byte lanes to update in memory. |
| S_AXI_CTRL_WVALID | NA | I | Write valid. This signal indicates that valid write data and strobes are available. |
| S_AXI_CTRL_WREADY | NA | O | Write ready. This signal indicates that the slave can accept the write data. |
| AXI Write Response Channel Signals | |||
| S_AXI_CTRL_BRESP | 1:0 | O |
Write response. This signal indicates the status of the write transaction. 00 - OKAY 10 - SLVERR 11 - DECERR |
| S_AXI_CTRL_BVALID | NA | O | Write response valid. This signal indicates that a valid write response is available. |
| S_AXI_CTRL_BREADY | NA | I | Response ready. This signal indicates that the master can accept the response information. |
| AXI Read Address Channel Signals | |||
| S_AXI_CTRL_ARADDR | C_S_AXI_CTRL_ADDR_WIDTH-1:0 | I | Read address. The read address bus gives the address of a read transaction. |
| S_AXI_CTRL_ARVALID | NA | I | Read address valid. This signal indicates, when HIGH, that the read address is valid and remains stable until the address acknowledgment signal, S_AXI_CTRL_ARREADY, is High. |
| S_AXI_CTRL_ARREADY | NA | O | Read address ready. This signal indicates that the slave is ready to accept an address. |
| AXI Read Data Channel Signals | |||
| S_AXI_CTRL_RDATA | C_S_AXI_CTRL_DATA_WIDTH-1:0 | O | Read data |
| S_AXI_CTRL_RRESP | 1:0 | O |
Read response. This signal indicates the status of the read transfer. 00 - OKAY 10 - SLVERR 11 - DECERR |
| S_AXI_CTRL_RVALID | NA | O | Read valid. This signal indicates that the required read data is available and the read transfer can complete |
| S_AXI_CTRL_RREADY | NA | I | Read ready. This signal indicates that the master can accept the read data and response information |