Data read from on-chip RAM is available on the clock cycle after the address strobe is asserted when a single port is used. This is also true when single bit errors are corrected. Data write is performed on the clock cycle after the address strobe is asserted, when a single port is used.
When ECC is enabled with 32-bit data width, byte and half word data writes add a two cycle latency to the write access. This is to perform a read-modify-write cycle to generate proper ECC for the full 32-bit word stored in on-chip RAM. With 64-bit data width, word writes also add the two cycle latency.
When multiple ports are used, latency is increased when an access has to wait until an ongoing access on another port with higher priority is completed.