LMB Controller With Protection - LMB Controller With Protection - 4.0 English - PG112

LMB Block RAM Interface Controller LogiCORE IP Product Guide (PG112)

Document ID
PG112
Release Date
2025-11-20
Version
4.0 English

The LMB block RAM Interface Controller can be configured to restrict allowed accesses when one or more of the masters connected to a port provide the optional LMB_Prot signal. The respective port configuration parameter C_PROT_CFG, C_PROT_CFG1 – C_PROT_CFG7 defines if read or write access is allowed for each of the four possible LMB_Prot signal values, as shown in the following table.

Table 1. LMB_Prot Signal Values
Access LMB_Prot Value C_PROT_CFG Bit Description

Data Read

Instruction Read
00 0 Read allowed when set to 1
01 1
10 2
11 3
Data Write 00 4 Write allowed when set to 1
01 5
10 6
11 7

Typical configurations with different LMB masters are exemplified in the following table.

Master Privilege Mode Access C_PROT_CFG Binary Value
MicroBlaze Privileged Only DLMB Read Write 0010 0010

DLMB Read Only

ILMB Execute

0010 0000
User Only DLMB Read Write 0100 0100

DLMB Read Only

ILMB Execute

0100 0000
Privileged and User DLMB Read Write 01100110

DLMB Read Only

ILMB Execute

01100000
MicroBlaze V Machine Only DLMB Read Write 0010 0010

DLMB Read Only

ILMB Execute

0010 0000
User Only DLMB Read Write 0100 0100

DLMB Read Only

ILMB Execute

0100 0000
Supervisor Only DLMB Read Write 0001 0001

DLMB Read Only

ILMB Execute

0001 0000
User and Supervisor DLMB Read Write 0101 0101

DLMB Read Only

ILMB Execute

0101 0000
AXI LMB Bridge Privileged Read Write 0010 0010
Read Only 0010 0000
Unprivileged Read Write 0100 0100
Read Only 0100 0000