LMB Controller With ECC - LMB Controller With ECC - 4.0 English

To mitigate the effect of on-chip RAM Single Event Upsets (SEU), the LMB Block RAM Interface Controller can be configured to use Error Correction Codes (ECC). When writing to the on-chip RAM, ECC bits are generated and stored together with the written data. When reading from the on-chip RAM, the ECC bits are used to correct all single bit errors and detect all double bit errors in the data read. Errors are either signaled by the LMB to MicroBlaze or by an interrupt signal. The ECC used with 32-bit data width is a (32,7) Hamming code, as defined in the following table, whereas the ECC used with 64-bit data width is a (64,8) Hamming code, as defined in Table 3.

Table 1. ECC (32,7) Coding
Participating Data Bits	ECC0 (MSB)	ECC1	ECC2	ECC3	ECC4	ECC5	ECC6 (LSB)
0 - Most Significant Bit (MSB)	*	*					*
1	*		*				*
2		*	*				*
3	*	*	*
4	*			*			*
5		*		*			*
6	*	*		*
7			*	*			*
8	*		*	*
9		*	*	*
10	*	*	*	*			*
11	*				*		*
12		*			*		*
13	*	*			*
14			*		*		*
15	*		*		*
16		*	*		*
17	*	*	*		*		*
18				*	*		*
19	*			*	*
20		*		*	*
21	*	*		*	*		*
22			*	*	*
23	*		*	*	*		*
24		*	*	*	*		*
25	*	*	*	*	*
26	*					*	*
27		*				*	*
28	*	*				*
29			*			*	*
30	*		*			*
31 - Least Significant Bit (LSB)		*	*			*

The ECC encoding corresponds to that shown in the AMD Application Note, Single Error Correction and Double Error Detection (XAPP645). However, it is shown here in its optimized form.

Table 2. ECC (64,8) Coding
Participating Data Bits	ECC0 (MSB)	ECC1	ECC2	ECC3	ECC4	ECC5	ECC6	ECC7 (LSB)
0 - 31	From Table 3-1: ECC0 - ECC5							ECC6
32	*	*	*			*		*
33				*		*		*
34	*			*		*
35		*		*		*
36	*	*		*		*		*
37			*	*		*
38	*		*	*		*		*
39		*	*	*		*		*
40	*	*	*	*		*
41					*	*		*
42	*				*	*
43		*			*	*
44	*	*			*	*		*
45			*		*	*
46	*		*		*	*		*
47		*	*		*	*		*
48	*	*	*		*	*
49				*	*	*
50	*			*	*	*		*
51		*		*	*	*		*
52	*	*		*	*	*
53			*	*	*	*		*
54	*		*	*	*	*
55		*	*	*	*	*
56	*	*	*	*	*	*		*
57	*						*	*
58		*					*	*
59	*	*					*
60			*				*	*
61	*		*				*
62		*	*				*
63 - Least Significant Bit (LSB)	*	*	*				*	*

The need to store the ECC increases the on-chip RAM utilization depending on the RAM data size. The overhead with 32-bit data width is listed in the following table.

Table 3. ECC Overhead
Block RAM Data Size	Ultra RAM Data Size	ECC Overhead
4 kB	32 kB	100%
8 kB	64 kB	50%
16 kB and larger	128 kB and larger	25%

A set of optional registers in the LMB block RAM Interface Controller controls the operation of the ECC logic. The registers are accessed through an AXI4-Lite slave interface. The slave interface is connected to MicroBlaze M_AXI_DP ports in a typical system, according to the following figure.

The LMB block RAM Interface Controller requires that the AXI4-Lite bus is synchronous to LMB_Clk.

Figure 1. Typical MicroBlaze System Using ECC

LMB Controller With ECC - LMB Controller With ECC - 4.0 English - PG112

LMB Block RAM Interface Controller LogiCORE IP Product Guide (PG112)