Instruction Prefetch - Instruction Prefetch - 4.0 English - PG112

LMB Block RAM Interface Controller LogiCORE IP Product Guide (PG112)

Document ID
PG112
Release Date
2025-11-20
Version
4.0 English

MicroBlazeâ„¢ can perform instruction prefetch and subsequently discard the prefetched instructions if a branch occurs. If any prefetched data has an uncorrectable error, the processor execution is not affected. However, the LMB block RAM Interface Controller registers are updated and the external UE signal is asserted.