| AMD LogiCORE™ IP Facts Table | |
|---|---|
| Core Specifics | |
| Supported Device Family 1 |
AMD Versal™
Adaptive
SoC AMD UltraScale+™ AMD UltraScale™ AMD Zynq™ 7000 SoC 7 series |
| Supported User Interfaces | LMB, AXI4-Lite |
| Resources | Performance and Resource Use web page |
| Provided with Core | |
| Design Files | AMD Vivado™ : Register Transfer Lever (RTL) |
| Example Design | Not Provided |
| Test Bench | Not Provided |
| Constraints File | Not Provided |
| Simulation Model | VHDL Behavioral |
| Supported S/W Driver 2 | Standalone |
| Tested Design Flows 3 | |
| Design Entry | AMD Vivado™ Design Suite |
| Simulation | For supported simulators, see the Vivado Design Suite User Guide: Release Notes, Installation, and Licensing (UG973). |
| Synthesis | AMD Vivado™ Synthesis |
| Support | |
| Release Notes and Known Issues | Master Answer Record: 54407 |
| All AMD Vivado™ IP Change Logs | Master AMD Vivado™ IP Change Logs: 72775 |
| Support web page | |
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