This section provides debug steps for common issues. The Vivado Design Suite debug feature is a valuable resource to use in hardware debug. The signal names mentioned in the following individual sections can be probed using the debug feature to debug specific problems.
Many of these common issues can also be applied to debugging design simulations.
General Checks
Ensure that all the timing constraints were met during implementation.
- Does it work in post-place and route timing simulation? If problems are seen in hardware but not in timing simulation, this could indicate a PCB issue. Ensure that all clock sources are active and clean.
- If using MMCMs in the design, ensure that all MMCMs have
obtained lock by monitoring the
LOCKEDport.
LMB Checks
To monitor the LMB interface, the signals
LMB_ABus, LMB_WriteDBus,
LMB_ReadStrobe, LMB_AddrStrobe,
LMB_WriteStrobe, LMB_BE, Sl_DBus, and
Sl_Ready can be connected to the Vivado debug feature.
When Error Correction Codes are used, the signals l_Wait, Sl_CE, and
Sl_UE can also be added.
To sample the interface signals, the Vivado
debug feature should use the LMB_Clk clock signal.