In an MicroBlaze™ or MicroBlaze V system without Error Correction Codes (ECC) protection, the LMB block RAM Interface Controller is typically connected as in shown in following figure.
The Interrupt output and the AXI4-Lite interfaces are unconnected, and the BRAM_DIn_A and BRAM_DOut_A signals contain 32 or 64 data bits.
The LMB Block RAM Interface Controller supports multiple LMB masters, making it possible to use the second on-chip RAM port for low latency data communication with MicroBlaze. The LMB Interface Controller would in this case be connected, as in shown in following figure.
MicroBlaze™ performance drops somewhat, because the DLMB and ILMB accesses now cannot be performed concurrently. The performance reduction is application dependent, but can be expected to be 10–20%.
When the LMB Block RAM Interface Controller supports more than one master, there is a fixed priority order between the LMB ports. SLMB has the highest priority in decreasing priority order, SLMB1, SLMB2, and SLMB3. To minimize the negative performance impact MicroBlaze™ DLMB should be given the highest priority, which means that it should be connected to SLMB and MicroBlaze™ ILMB to SLMB1.
When using Ultra RAM in UltraScale+ devices, it is not possible to initialize the memory with an ELF file. In this case, a configuration with Multiplexed ILMB and DLMB can be used to initialize the memory, while MicroBlaze is reset or sleeping before starting execution. Another possible configuration is a combination of block RAM with boot software and an Ultra RAM.