This system uses all features provided by the LMB block RAM Interface Controller to enable full error injection capability as well as error monitoring and interrupt generation. This is a typical system with the addition of Uncorrectable Error First Failing registers and Fault Injection registers. All features are switched on for full control of ECC functionality for system debug or systems with high fault tolerance requirements. Parameters set are C_ECC = 1, C_CE_COUNTER_WIDTH = 10, C_ECC_STATUS_REGISTER = 1, C_CE_FAILING_REGISTERS = 1, C_UE_FAILING_REGISTERS = 1, and C_FAULT_INJECT = 1.