Features - Features - 4.0 English - PG112

LMB Block RAM Interface Controller LogiCORE IP Product Guide (PG112)

Document ID
PG112
Release Date
2025-11-20
Version
4.0 English
  • LMB v1.0 bus interfaces with byte enable support.
  • Used with the Block Memory Generator or Embedded Memory Generator core to provide a fast on-chip RAM memory solution for MicroBlaze ILMB and DLMB ports.
  • Supports byte, halfword, and word transfers.
  • Supports optional error correction and detection.
  • Supports multiple LMB masters with static priority and round-robin arbitration.
  • Support for an extended address up to 64 bits.
  • Support for 32-bit and 64-bit data width.