Provides a low area, high frequency, and low latency connection for the MicroBlaze DLMB and ILMB ports to device block RAM or Ultra RAM. Ultra RAM is only available on AMD UltraScale+™ and AMD Versal™ devices. The supported on-chip RAM sizes are determined by the Block Memory Generator core or Embedded Memory Generator core on AMD Versal™ devices, (nominally 4 KB or more), with the possibility of performing 32-bit word, 16-bit half word, as well as byte accesses.
Error Correction Codes (ECC) is available as an option for providing a solution suitable for applications with higher reliability requirements. When enabled, the ECC function corrects all single bit errors and detects all double bit errors. A set of optional ECC control and status registers are available, making it possible to tailor the ECC function to meet different requirements on ECC error injection, monitoring, and signaling. The optional ECC registers are connected to MicroBlaze™ through an AXI4-Lite interface.
The LMB Block RAM Interface Controller core supports multiple LMB masters, making it possible to use only one of the ports of the on-chip RAM. This allows the other port of the on-chip RAM to be used for low latency/low overhead data movement to and from MicroBlaze local memory.
When a connected LMB master implements support for LMB protection, the LMB block RAM Interface Controller can be configured to restrict allowed accesses, for example, only privileged accesses or only read accesses.
When MicroBlaze is configured to use an extended data address from 32 to 64 bits, the dataside LMB Block RAM Interface Controller uses the extended address to determine if the local memory is accessed.
When MicroBlaze is configured to use 64-bit LMB data width, the LMB Block RAM Interface Controller uses 64-bit data width. If ECC is enabled, the error correction code uses eight bits.