Example Base Address, High Address Specifications - Example Base Address, High Address Specifications - 4.0 English - PG112

LMB Block RAM Interface Controller LogiCORE IP Product Guide (PG112)

Document ID
PG112
Release Date
2025-11-20
Version
4.0 English

The base address (C_BASEADDR) and high address (C_HIGHADDR) must specify a valid range for the on-chip RAM that is attached to the LMB Block RAM Interface Controller. The range (C_HIGHADDR–C_BASEADDR) specified by the Offset Address and Range in Vivado IP integrator must be equal to 2n bytes, where n is a positive integer and 2n is a valid memory size as shown above. In addition, the n least significant bits of C_BASEADDR must be equal to 0.