This register holds information about correctable and uncorrectable errors. The status bits are independently set to 1 for the first occurrence of each error type. The status bits are cleared by writing a 1 to the corresponding bit position, that is, the status bits can only be cleared to 0 and not set to 1 by means of a register write. The ECC Status register operates independently of the ECC Enable Interrupt register.
The register is implemented if C_ECC_STATUS_REGISTERS is set to 1.
| Reserved | ECC_STATUS | ||
|---|---|---|---|
| 31 | 2 | 1 | 0 |
| Bit(s) | Name | Core Access | Reset Value | Description |
|---|---|---|---|---|
| 1 | CE_STATUS | R/W | 0 |
If 1, a correctable error has occurred. Cleared when 1 is written to this bit position |
| 0 | UE_STATUS | R/W | 0 |
If 1, an uncorrectable error has occurred. Cleared when 1 is written to this bit position |