ECC Interrupt Enable Register (ECC_EN_IRQ) - ECC Interrupt Enable Register (ECC_EN_IRQ) - 4.0 English

ECC Interrupt Enable Register (ECC_EN_IRQ) - ECC Interrupt Enable Register (ECC_EN_IRQ) - 4.0 English - PG112

LMB Block RAM Interface Controller LogiCORE IP Product Guide (PG112)

Document ID

PG112

Release Date

2025-11-20

Version

4.0 English

This register determines if the value of the CE_STATUS and UE_STATUS bits of the ECC Status Register asserts the Interrupt output signal. If both CE_EN_IRQ and UE_EN_IRQ are set to 1 (enabled), the value of the Interrupt signal is the logical OR between the CE_STATUS and UE_STATUS bits.

The register is implemented if C_ECC_STATUS_REGISTERS is set to 1.

Table 1. ECC Interrupt Enable Register (ECC_EN_IRQ)
Reserved		ECC_EN_IRQ
31	2	1	0

Table 2. ECC Interrupt Enable Register Bit Definitions
Bit(s)	Name	Core Access	Reset Value	Description
1	CE_EN_IRQ	R/W	0	If 1, the value of the CE_STATUS bit of the ECC Status Register is propagated to the Interrupt signal. if 0, the value of the CE_STATUS bit of ECC Status Register is not propagated to the Interrupt signal.
0	UE_EN_IRQ	R/W	0	If 1, the value of the UE_STATUS bit of ECC Status Register is propagated to the Interrupt signal. if 0, the value of the UE_STATUS bit of ECC Status Register is not propagated to the Interrupt signal.