Customizing and Generating the Core - Customizing and Generating the Core - 4.0 English

This section includes information about using AMD tools to customize and generate the core in the Vivado Design Suite.

If you are customizing and generating the core in the Vivado IP integrator, see Vivado Design Suite User Guide: Designing IP Subsystems using IP Integrator (UG994) for detailed information. IP integrator might auto-compute certain configuration values when validating or generating the design. To check whether the values do change, see the description of the parameter in this chapter. To view the parameter value, run the validate_bd_design command in the Tcl Console.

You can customize the IP for use in your design by specifying values for the various parameters associated with the IP core using the following steps:

Select the IP from the Vivado IP catalog.
Double-click the selected IP or select the Customize IP command from the toolbar or right-click menu.

For details, see the Vivado Design Suite User Guide: Designing with IP (UG896) and the Vivado Design Suite User Guide: Getting Started (UG910).

Note: Figures in this chapter are illustrations of the Vivado Integrated Design Environment (IDE). The layout depicted here might vary from the current version.

The LMB block RAM Interface Controller parameters are divided into two categories: Addresses and ECC. When using the Vivado IP integrator feature, the addresses and masks are auto-generated.

The Addresses parameter configuration screen is shown in the following figure.

Figure 1. Addresses Parameter Tab

Number of LMB Ports: Sets the number of ports available to connect to MicroBlaze™ .
LMB Arbitration: Defines the arbitration scheme when more than one LMB port is used. With STATIC_PRIORITY, the lowest numbered port requesting an access is selected, whereas ROUND ROBIN selects the ports in a circular order.
Write Access Setting: Can be set to Full, Word only, or None. Should normally be set to Full.
LMB Block RAM Base Address: Base address of the local memory with up to 64 bits.
LMB Block RAM High Address: High address of the local memory with up to 64 bits.
SLMB/SLMB1-SLMB7 Address Decode Mask: A mask indicating which address bits the LMB Block RAM Interface Controller considers when decoding an access with up to 64 bits.

SLMB/SLMB1-SLMB7 Protection Configuration: A mask indicating which of the LMB protection values are allowed.

The ECC parameter configuration screen is shown in the following figure.

Figure 2. ECC Parameter Tab

Error Correction Code: Enables Error Correction Code to correct single bit errors and detect double bit errors.
Select Interconnect: Can be set to None for basic functionality or AXI to access ECC registers.
Fault Inject Registers: Enable fault inject registers to allow testing of the ECC functionality.
Correctable Error First Failing Register: Enable this register to store the first failing address of a correctable error.
Uncorrectable Error First Failing Register: Enable this register to store the first failing address of an uncorrectable error.
ECC Status and Control Register: Enable these registers to read the ECC status and control ECC generation.
ECC On/Off Register: Enable this register to be able to toggle the ECC functionality.
ECC On/Off Reset Value: Set to 1 to enable the ECC or 0 to disable the ECC after reset.
Correctable Error Counter Register Width: Determines how many correctable errors can be counted. The value 0 means that the register is not implemented.

Customizing and Generating the Core - Customizing and Generating the Core - 4.0 English - PG112

LMB Block RAM Interface Controller LogiCORE IP Product Guide (PG112)