Correctable Error First Failing ECC Register (CE_FFE) - Correctable Error First Failing ECC Register (CE_FFE) - 4.0 English - PG112

LMB Block RAM Interface Controller LogiCORE IP Product Guide (PG112)
Document ID
PG112
Release Date
2025-11-20
Version
4.0 English

This register stores the ECC of the first occurrence of an access with a correctable error. When the CE_STATUS bit in the ECC Status Register is cleared, this register is re-enabled to store the ECC of the next correctable error. Storing of the failing ECC is enabled after reset.

The register is implemented if C_CE_FAILING_REGISTERS is set to 1.

Table 1. Correctable Error First Failing ECC Register (CE_FFE)
Reserved CE_FFE
31   7 or 6 0
Table 2. Correctable Error First Failing ECC Register Bit Definitions
Bit(s) Name Core Access Reset Value Description
7:0 or 6:0 CE_FFE R 0 ECC of the first occurrence of a correctable error. CE_FFE is eight bits with 64-bit data width and seven bits with 32-bit data width.