This register stores the (uncorrected) failing data of the first occurrence of an access with a correctable error. When the CE_STATUS bit in the ECC Status Register is cleared, this register is re-enabled to store the data of the next correctable error. Storing of failing data is enabled after reset.
The register is implemented if the C_CE_FAILING_REGISTERS is set to 1.
| CE_FFD | |
|---|---|
| C_LMB_DWIDTH-1 | 0 |
| Bit(s) | Name | Core Access | Reset Value | Description |
|---|---|---|---|---|
| C_LMB_DWIDTH-1:0 | CE_FFD | R | 0 | Data of the first occurrence of a correctable error. The register is 64 bits with 64-bit data width and 32 bits with 32-bit data width. |