This register stores the address of the first occurrence of an access with a correctable error. When the CE_STATUS bit in the ECC Status Register is cleared, this register is re-enabled to store the address of the next correctable error. Storing of the failing address is enabled after reset. When the address width is greater than 32 bits, the most significant bits of the LMB address are read from register address 0x1C4. The register reports the failing word address.
The register is implemented if C_CE_FAILING_REGISTERS is set to 1.
| CE_FFA | |
|---|---|
| C_LMB_AWIDTH-1 | 0 |
| Bit(s) | Name | Core Access | Reset Value | Description |
|---|---|---|---|---|
| C_LMB_AWIDTH-1:0 | CE_FFA | R | 0 | Address of the first occurrence of a correctable error |