The LMB Block RAM Interface Controller core is the interface between the LMB and the AMD Block Memory Generator core, or the Embedded Memory Generator core for AMD Versal™ Adaptive SoCs. An on-chip RAM memory subsystem consists of the controller and the bram_block peripheral, the Block Memory Generator core, or Embedded Memory Generator core.
The input/output signals of the LMB Block RAM Interface Controller core are shown in following figure. The detailed list of signals are listed and described in Table 1 . See the description of LMB Signals in the MicroBlaze Bus Interfaces chapter in the MicroBlaze Processor Reference Guide (UG984) or the MicroBlaze V Processor Reference Guide (UG1629).