C_INTERCONNECT - C_INTERCONNECT - 4.0 English - PG112

LMB Block RAM Interface Controller LogiCORE IP Product Guide (PG112)

Document ID
PG112
Release Date
2025-11-20
Version
4.0 English

When error correction and detection are enabled (C_ECC = 1) and any register parameters are enabled, an interface to access the registers is needed. The register access interface can be of AXI4-Lite type. The parameters related to AXI4-Lite are ‘don’t care’ unless enabled by the value of C_INTERCONNECT.