AXI4-Lite Interface Debug - AXI4-Lite Interface Debug - 4.0 English - PG112

Read from a register that does not have all 0s as a default to verify that the interface is functional. Output S_AXI_CTRL_ARREADY asserts when the read address is valid, and output S_AXI_CTRL_RVALID asserts when the read data/response is valid. If the interface is unresponsive, ensure that the following conditions are met:

• The S_AXI_CTRL_ACLK input is connected and toggling.
• The interface is not being held in reset, and S_AXI_CTRL_ARESETN is an active-Low reset.
• The main core clock LMB_Clk is toggling and that the enables are also asserted.
• If the simulation has been run, verify in simulation and/or a Vivado debug capture that the waveform is correct for accessing the AXI4-Lite interface.